Category: addressable-latch 

An addressable latch is a digital storage element that allows one of several latch cells to be individually selected and updated using an address input, while all others remain unchanged. It typically combines a bank of simple latches with a decoder so that only the latch corresponding to the active address line responds to the data and enable signals. This structure makes it efficient for building small register files, configuration registers, or memory-mapped control blocks, because a single shared data path can write to many storage locations without needing separate control lines for each one.

 

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Internal identifier: logic.addressable-latch - Created: 2026-02-12 16:36:16